The present invention relates to multi-chip modules that include a plurality of semiconductor chips having a plurality of connection pads and that are implemented by electrically connecting the associated connection pads to each other between the semiconductor chips. The present invention also relates to semiconductor chips for use in forming such multi-chip modules, and test methods for the connection between the semiconductor chips in the multi-chip modules.
In recent years, the concept of a so-called one-chip system LSI in which a plurality of functional elements are formed on a common substrate has been introduced, and various propositions have been made for methods of designing such system LSIs. In particular, the advantage of the one-chip system LSI is that a variety of functional elements such as a memory (e.g., DRAM or SRAM), a logic circuit, and an analogue circuit can be integrated on a single semiconductor chip, thus implementing a high-performance and multifunction device. However, in implementing such a device, the system LSI is confronted with two problems as described below.
A first problem is that the increase in the size of the system LSI requires considerable development efforts and the fabricating cost of the device is increased because its fabricating yield is reduced due to an increase in chip area.
A second problem is that it is hard to carry out the process of combining different types of devices (including a DRAM and a flash memory, for example) on a chip in coordination with the process of fabricating a pure CMOS, thus making it very difficult to put both the processes into practice at the same time. Therefore, the process of combining different types of devices on a chip falls behind the most advanced pure CMOS fabricating process in development for about one or two years, which prevents production and supply from timely meeting the needs of the market.
To cope with the above-described problems, Japanese Unexamined Patent Publication No. 58-92230 proposes a chip-on-chip type system LSI implemented by modularizing a plurality of semiconductor chips. In the technique of forming the chip-on-chip multi-chip module, a connection pad electrode provided on a semiconductor chip to which another semiconductor chip will be connected (hereinafter called a “master semiconductor chip”), and a connection pad electrode provided on said another semiconductor chip which is to be connected to the master semiconductor chip (hereinafter called “a slave semiconductor chip”) are each formed as a bump. By connecting the connection pad electrodes between both the semiconductor chips, an electrical connection is made between the semiconductor chips, thereby modularizing a plurality of semiconductor chips.
Unlike the one-chip system LSI, the chip-on-chip type system LSI performs its functions in a distributed manner using a plurality of semiconductor chips, and thus each semiconductor chip can be reduced in size to improve its yield. Further, since even different types of devices of different process generations can be easily modularized, it is possible to expand the functions of the module. In addition, since the system LSI obtained by using the above-described technique of forming a chip-on-chip type multi-chip module has extremely shorter wiring length needed for an interface between master and slave chips compared to that provided by the other techniques of forming a multi-chip module, an interface through which high-speed signal transmission is allowed can be achieved. In this case, the interface can give the performance equivalent to that given by the interface between blocks in a conventional one-chip system LSI.
Although the above-described technique of forming a chip-on-chip type multi-chip module is a very important technique with which multi-chip modules replace conventional one-chip system LSIs, this technique has the following problems.
That is, as the technique of forming a chip-on-chip type multi-chip module is more widely used in the future, it is conceivable that a manufacturer of semiconductor chips and a manufacturer in charge of packaging and manufacturing multi-chip modules could be different. In such a case, it is impossible to determine, by using a total function test with which the quality of a whole multi-chip module is determined, whether a failure in the resulting multi-chip module is an internal failure or a connection failure caused between semiconductor chips during the packaging process. Thus, it is impossible to clarify which of the manufacturers is responsible for the failure. Therefore, it is desirable that a connection test for determining the quality of connection during a packaging process, i.e., the quality of the connection between semiconductor chips, easily at a low cost should be proposed in the near future.
An example of conventional tests for the connection between semiconductor chips is disclosed in Japanese Unexamined Patent Publication No. 2000-258494. It should be noted that in this description, the drawing (FIG. 1) of the publication is partly shown in FIGS. 7A through 7C to make it easier to understand the contents of the invention disclosed in the publication. How the test is performed will be described below with reference to FIGS. 7A through 7C.
FIG. 7A illustrates the case where a signal terminal 1-11 of an internal circuit 1-1 in a semiconductor chip 1 and a signal terminal 2-11 of an internal circuit 2-1 in a semiconductor chip 2 can be electrically connected to each other by electrically connecting a connection pad 1-21 and a connection pad 2-21 to each other, thus implementing a multi-chip module using the two semiconductor chips 1 and 2. In the publication, as shown in FIG. 7B, a connection pad 1-22 and two probing pads 1-01 and 1-02 are newly provided on the semiconductor chip 1 while a connection pad 2-22 is newly provided on the semiconductor chip 2 in order to carry out an interchip connection test on the connection between the connection pads 1-21 and 2-21. The two connection pads 2-21 and 2-22 of the semiconductor chip 2 are electrically connected to each other inside the semiconductor chip 2. When the two semiconductor chips 1 and 2 are connected by forming a chip-on-chip structure, the state of the electrical connection made between the semiconductor chips 1 and 2 are as shown in FIG. 7C. In this case, as can be seen from FIG. 7C, the two probing pads 1-01 and 1-02 are brought into conduction via the connection pads 1-22, 2-22, 2-21 and 1-21. Therefore, by measuring the impedance between both the probing pads 1-01 and 1-02, the quality of the electrical connection between the two connection pads 1-21 and 2-21 can be determined.
However, in the configuration shown in the Japanese Unexamined Patent Publication No. 2000-258494, the two connection pads 1-22 and 2-22 are needed to determine the quality of the connection at only one place, i.e., between the two connection pads 1-21 and 2-21. Furthermore, the two probing pads 1-01 and 1-02 are required to carry out a probing test. In general, probing pads are extremely larger in area than connection pads used for a chip-on-chip multi-chip module. In the configuration shown in the above publication, if the number of signals transmitted between the semiconductor chips stands at several hundreds to several thousands, the number of probing pads needs to be twice as much as that of the signals transmitted between the chips. Therefore, the technique described in the publication can no longer be applied due to the problems of the increase in the area of the probing pads and the complication of a prober itself.